1. Field of Invention
This invention is related to computer-aided design (CAD) logic verification tools, and more specifically to enabling a methodology which allows verification of circuit designs containing memories at multiple abstraction levels. For example, both equivalency checking and system-level verification can be performed efficiently.
2. Background of Invention
Verification of digital circuit designs such as microprocessors, application specific integrated circuits (ASICs), and system-on-a-chip (SOC) designs, conventionally involves two major steps termed as implementation verification and system-level verification.
The goal of implementation verification is to show that a register transfer language (RTL) abstraction of the design is logically equivalent to a low-level design implementation that is represented at the gate-level or the transistor-level (FIG. 1). The task of determining logic equivalence verifies that the RTL abstraction and the low-level designs implement equivalent finite state machines. This task is generally performed today by using formal equivalence checkers, and requires a methodology where RTL abstraction and the design implementations have similar state machine encoding, and/or design hierarchy.
The goal of system-level verification is to verify the high-level operations the design has to perform, and the overall functionality of the design in context of the system in which it is used. This task is performed by logic simulation of the design RTL in a system-level testbench (FIG. 1).
Today, modern digital systems contain multiple embedded memories of increasing size and complexity which make the tasks of implementation and system-level verification difficult and increases the risks of functional failures in the design. The basic reason for this verification difficulty is that implementation verification via a formal equivalence checker requires that the embedded memories in the RTL have a structure which closely follows that of the low-level design implementation, e.g., both RTL and design implementations should have identical memory cell row-column organization. Furthermore, some circuit behavior cannot be easily described at the RTL-level and may require extensive transistor/logic remodeling in the low-level implementation.
So, to make equivalence checking of embedded memories possible, one may with some effort create an RTL memory model which matches the implementation structure and models its circuit behavior. Unfortunately, such a detailed model is very expensive to simulate as compared to a conventional RTL memory model which does not describe detailed internal memory structure. A need exists for an efficient verification of memory at multiple abstraction levels.